NDLI: Multi chip stacking & reliability challenges using TSV-micro C4 solder interconnection for FCCSP TSV package

Content Provider	IEEE Xplore Digital Library
Author	Au, K.Y. Beleran, J.D. Yang, Y.B. Zhang, Y.F. Kriangsak, S.L. Wilson, P.L.O. Drake, Y.S.K. Nathapong, S.
Copyright Year	2011
Description	Author affiliation: United Test and Assembly Center Ltd (UTAC), 5 Serangoon North Ave 5, Singapore 554916 (Au, K.Y.; Beleran, J.D.; Yang, Y.B.; Zhang, Y.F.; Kriangsak, S.L.; Wilson, P.L.O.; Drake, Y.S.K.; Nathapong, S.)
Abstract	Through silicon via (TSV) is a three-dimensional packaging technology involving vertical chips stacking using metal-filled via holes and bumps. TSV stacked chip drastically reduces interconnect distance than conventional multi-stack wire bond silicon chips, enabling faster speeds, lower power consumption and smaller microelectronic package size for 22nm tech node and below. TSI (Thru Silicon Interposer) enables interconnect pitch matching between a high I/Os top chip and low cost organic substrate and is crucial in mitigating risks of low K layer delamination and provide additional routing capability to enable the use of low cost organic substrate. This paper demonstrate with aid from finite element analysis, the daunting processibility challenges and reliability performance for a 2 die and 4 die thin die stacking on a strip organic substrate using standard flip chip machines in a mass production scenario. Critical factors such as 1× versus 2× reflow process flow, material properties fundamentals, bill of material (BOM), substrate & package structure design and its influence on thermo-mechanical stress, package warpage and joint cracks in conjunction with process breakthrough to enable multiple die stacking, multi-gap flux cleaning and capillary underfilling will be discussed in great details. In addition, Micro C4 solder bumps joints with TiW/Cu/Ni under bumps metallization (UBM) and TiW/Cu/Ni/Au bond pad were shown to be reliable with integrity of the UBM with regards to IMC growth and solder diffusion up to 1000 thermal cycles. Establishment of all these fundamental capabilities is required to strengthen the low cost high volume production capability for thru silicon stacking (TSS).
Starting Page	608
Ending Page	619
File Size	12559485
Page Count	12
File Format	PDF
ISBN	9781457719837
e-ISBN	9781457719820
e-ISBN	9781457719813
DOI	10.1109/EPTC.2011.6184493
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-12-07
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Stress Substrates Silicon Through-silicon vias Stacking Assembly Joints
Content Type	Text
Resource Type	Article

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