NDLI: Underfill characterization for multi-layer 3D-SiP stacked chip package

Content Provider	IEEE Xplore Digital Library
Author	Chew, M. Wai, E. Chew Tham Heang Ho, D. Lim, S. Ser Choong Chong Chai, T.C. Rao, V.S.
Copyright Year	2011
Description	Author affiliation: Infineon Technologies Asia Pacific Pte Ltd, IFAP OP BE PTI UPD, 168 Kallang Way, Singapore 349253 (Chew Tham Heang) \|\| Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), 11 Science Park Road, Singapore Science Park II, Singapore 117685 (Chew, M.; Wai, E.; Ho, D.; Lim, S.; Ser Choong Chong; Chai, T.C.; Rao, V.S.)
Abstract	In this paper, evaluation of underfill materials for 3D SiP packages where micro bump interconnections and solder bumps has been presented. Characterization of underfill materials was carried out in terms of adhesion testing on various chip passivation surfaces and process optimization for void free filling. Capillary underfill materials have been evaluated for micro bump interconnections for 3D stacked module with different size chips as well as 3D stacked module with same size chips, and moldable underfill has been evaluated for over molding of stacked module along with underfilling of solder bump interconnections. Die shear test was carried out on adhesion test samples and results revealed failure between chip and polyimide layers in polyimide samples, and mixed failure between underfill and passivation layer in SiN samples. Process optimization for void free underfilling for CUFs were carried out based on dispensing temperature, speed, length, pattern and effects of plasma treatments. For MUF, the transfer molding process optimization was carried out by varying transfer time and die temperature to achieve void free underfilling and molding process. CSAM and through scan analysis was carried out on the under filled samples to check the quality of the underfilling process. The optimized process results shown void free underfilling for both 3D stacked module packages with different size chips as well as same size chips.
Starting Page	462
Ending Page	468
File Size	1633687
Page Count	7
File Format	PDF
ISBN	9781457719837
e-ISBN	9781457719820
e-ISBN	9781457719813
DOI	10.1109/EPTC.2011.6184465
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-12-07
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Adhesives Passivation Materials Three dimensional displays Vehicles Delamination Plasmas
Content Type	Text
Resource Type	Article

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