NDLI: Near term solutions for 3D packaging of high performance DRAM

Content Provider	IEEE Xplore Digital Library
Author	Solberg, V. Zohni, W.
Copyright Year	2011
Description	Author affiliation: Invensas (a Tessera company), San Jose, California USA (Solberg, V.; Zohni, W.)
Abstract	The revolution in performance driven electronic systems continues to challenge the IC packaging industry. To enable the new generations of processors to reach their performance potential and to achieve greater memory density and bandwidth, many manufacturers have developed a number of two-die package interface formats. Effective 3D stacking of memory die elements can offer many benefits; improved performance, increased component density and greater surface area utilization. The methodology selected for package assembly, however, must consider process complexity, the costs associated with each process, overall package assembly yield and end product reliability. To ensure that the memory functions are able to support the increased signal speed of the new generations of memory, package developers are relying more and more on die-stack assembly techniques and process refinement. This paper briefly reviews current two-die package assembly methodologies for the high performance, synchronous dynamic random-access memory (SDRAM) and introduces, in greater detail, an innovative two-die, face-down package assembly developed specifically for the next generation center bond memory products.
Starting Page	39
Ending Page	43
File Size	794515
Page Count	5
File Format	PDF
ISBN	9781457719837
e-ISBN	9781457719820
e-ISBN	9781457719813
DOI	10.1109/EPTC.2011.6184382
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-12-07
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Assembly Substrates Surface treatment SDRAM Performance evaluation Gold Wires DFD DDP DRAM DDR3 DDR4
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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