NDLI: Decoupling capacitance for the power integrity of 3D-DRAM-over-logic system

Content Provider	IEEE Xplore Digital Library
Author	Ahmad, W. Qiang Chen Li-Rong Zheng Tenhunen, H.
Copyright Year	2011
Description	Author affiliation: Department of Electronics, Computer and Software Systems, KTH, School of Information and Communication Technologies, Forum 120,, 164 40 Kista, Sweden (Ahmad, W.; Qiang Chen; Li-Rong Zheng; Tenhunen, H.)
Abstract	The 3D-DRAM stacked over the processor is a vibrant technique in order to overcome the memory wall as well as the bandwidth wall problems. We considered a system with two DRAM dies over a single processor die. We assumed the decoupling capacitors to be placed on each DRAM die and connected to the power distribution TSV pairs, where the TSVs pass through the DRAM stack. In this paper we proposed a mathematical model for the optimum value of the decoupling capacitance on each DRAM die along with the optimum values of the effective resistance of the interconnecting power distribution TSV pairs in order to ensure the power integrity of the logic load during switching. The proposed model has a maximum of 1.1% error as compared to the Ansoft Nexxim4.1.
Starting Page	590
Ending Page	594
File Size	819047
Page Count	5
File Format	PDF
ISBN	9781457719837
e-ISBN	9781457719820
e-ISBN	9781457719813
DOI	10.1109/EPTC.2011.6184489
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-12-07
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Capacitance Through-silicon vias Power distribution Mathematical model Three dimensional displays Capacitors Power integrity Decoupling capacitance 3D-DRAM
Content Type	Text
Resource Type	Article

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