NDLI: The effect of stressing history in reliability characteristics

Content Provider	IEEE Xplore Digital Library
Author	Po-Ying Chen Heng-Yu Kung Yi-Shao Lai Wen-Kuan Yeh
Copyright Year	2006
Description	Author affiliation: Dept. of Inf. & Telecommun. Eng., Ming-Chuan Univ., Taipei (Po-Ying Chen)
Abstract	This paper applies an analysis of current flow to examine the current density destroy the architecture of wafer-level chip scale package (WLCSP). In package views, the CSP is very robust. Not only due to it had passed the JEDEC moisture level 1,1000 cycles of temperature cycling at level G from -40 to 125 degC and thermal shock test at level D from -65 to 150 degC. Derivatives from recent package technology (i.e. plastic ball grid arrays-PBGA, ceramic ball grid array-CBGA, chip scale package-CSP, etc.). New interconnection geometry was used extensively today with moderate success in overcoming larger mismatches in components displacements during current and temperature excursions. Meanwhile, both the environments and testing qualifications for these packages are becoming increasingly more and more demanding. Failure mechanisms thought to have been eliminated, or at least alleviated to some manageable extent in new package technology designs, are again challenge their process integrity and reliability. Especially for WLCSP, which was first designed to eliminate the need for encapsulation, to be smart mount technology (SMT) process compatible, and to have good handing properties, etc., face some serious reliability problems. Due to dynamic loading induced by mechanical vibration and impact shock results in reliability detractors for CSP package. Analytical models and simulation of some mechanisms were proposed. This paper investigated the reliability of a wafer-level chip-scale package (WLCSP) subjected to different accelerated current stressing conditions at a fixed ambient temperature of 125 degC. A reasonably good correlation between mean-time-to-failure (MTTF) of the WLCSP test vehicle and the average current density carried by a solder joint was obtained. Simultaneously, two steps current stressing method were used to clarify the characteristics in reliability property
Starting Page	576
Ending Page	581
File Size	659721
Page Count	6
File Format	PDF
ISBN	1424406641
DOI	10.1109/EPTC.2006.342777
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-12-06
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	History Chip scale packaging Wafer scale integration Temperature Testing Current density Electric shock Plastic packaging Electronics packaging Analytical models
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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