NDLI: Optimization of flip chip interconnect reliability using a variable compliance interconnect design

Content Provider	IEEE Xplore Digital Library
Author	Tay, A.A.O. Wei Sun
Copyright Year	2006
Description	Author affiliation: Dept. of Mech. Eng., Nat. Univ. of Singapore (Tay, A.A.O.; Wei Sun)
Abstract	This paper describes a finite element parametric study of the reliability of the solder joints of a flip chip package in which the height H and diameter D of copper column interconnects are varied. It was found that when D was kept constant at 50 mum while H was varied, from 25 mum to 150 mum, there was a local optimum at around H=50 mum. Thus while the compliance of the interconnect with H=100 mum was greater, it did not lead to a longer fatigue life. However, beyond H=125 mum, any increase in length/compliance did lead to a longer fatigue life. Similarly, when the interconnect height H was kept constant at 150 mum while the diameter D was varied from 15 mum to 35 mum, it was found that a local optimum existed at around D=25 mum. Next a simulation was conducted in which the height of the interconnects H was kept constant at 150mum while the diameter D on the same chip was decreased continuously from 35mum at the center to 15mum at the perimeter of the chip. It was found that this case where the compliance is low at the center and high at the perimeter of the chip gave fatigue lives which were more than double that of the local optimum case mentioned above where D was constant at 25mum. Hence, an interconnect design where the compliance of the interconnect on the same chip is varied from a low value at the center to a high value at the perimeter will lead to optimum reliability of the critical solder joint.
Starting Page	133
Ending Page	137
File Size	282199
Page Count	5
File Format	PDF
ISBN	1424406641
DOI	10.1109/EPTC.2006.342704
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-12-06
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Design optimization Flip chip Soldering Fatigue Packaging Copper Lead Tensile stress Temperature Finite element methods
Content Type	Text
Resource Type	Article

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