NDLI: Reliability improvement of 90nm large flip chip low-k die via dicing and assembly process optimization

Content Provider	IEEE Xplore Digital Library
Author	Chaware, R. Lan Hoang
Copyright Year	2006
Description	Author affiliation: Xilinx Inc., San Jose, CA (Chaware, R.; Lan Hoang)
Abstract	Increasing demand for higher processing speeds and enhanced electrical performance have made the use of low-k dielectric materials mandatory. For such low-k dielectric materials, enhanced dielectric properties are achieved via increased porosity of the low-k materials. These new low-k materials have different chemical, thermal, and mechanical properties than traditional dielectric materials used in older silicon technology, which in turn creates integration issues. The adhesion of the low-k layers in the silicon is also relatively weak. Due to their poor adhesion and brittle nature, low-k materials have a tendency to crack and chip during mechanical dicing with diamond blades, a widely used die singulation technique. In the case of field programmable gate array (FPGA) chips, as the demand for higher speeds and enhanced functionality increases, the size of the flip chip die grows accordingly to offer higher number of logic cells. Large flip chip die also requires a large package for efficient signal routing. Consequently, the stresses generated due to thermal expansion mismatch are severe, and even a small defect created on the edge of the chip during the dicing process can have a severe impact on the reliability of the flip chip device. To study the impact on flip chip reliability, two different laser dicing technologies were compared with the conventional mechanical dicing process. Other important variables tested during this study were dicing location in the saw street, lid attach dispense pattern, wafer lots, die size, and underfill. Reliability analysis indicated that for improvement of the reliability of the samples diced with mechanical dicing process, correct choice of underfill and lid attach material, optimization of the lid attach dispense pattern, and optimization of dicing location were required. In contrast, a wide reliability and process window was achieved by laser grooving process and none of the above factors tested during the study had any impact on the reliability.
Starting Page	622
Ending Page	626
File Size	375820
Page Count	5
File Format	PDF
ISBN	1424406641
DOI	10.1109/EPTC.2006.342785
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-12-06
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Flip chip Assembly Dielectric materials Chemical technology Silicon Adhesives Field programmable gate arrays Programmable logic arrays Thermal stresses Testing
Content Type	Text
Resource Type	Article

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