NDLI: New process of copper pillar bumps on substrate

Content Provider	IEEE Xplore Digital Library
Author	Yang Song Wenlong Liu Zhongyao Yu Xueping Guo Zhidan Fang Guowei Ding
Copyright Year	2014
Description	Author affiliation: Nat. Center for Adv. Packaging (NCAP China), Wuxi, China (Yang Song; Wenlong Liu; Zhongyao Yu; Xueping Guo; Zhidan Fang; Guowei Ding)
Abstract	With the miniaturization, multifunction, high speed development of the chip and package, the requirements for package substrate and 3D packaging becomes higher. As the IC line size continues to decrease, the signal transmission rate continues to improve and the amount and density of pin is getting more and more, the Pad pitch of package substrate which connects to it must be smaller and smaller. The development of package substrate on narrow pitch and low cost Copper pillar bump is becoming more and more important. Copper pillar bump has so many advantages in designs for the next generation of flip chip while it meets current and future ROHS requirements. This is a fabulous choice for actual application, such as transceivers, embedded processors, application processors, power management, baseband ASICs and SOCs where with connation of fine pitch, besides it meets ROHS/Green compliance, low cost and electromigration performance requirement. This article introduces how to process the high density interconnection and small pitch copper pillar bump organic substrate by modified semi-additive process. We have already designed and finished some test boards which narrates how to make copper pillar bump on organic substrate by modified semi-additive process, also it analysis on different packed structures in order to get proper design model, electrical and thermal test. Though these tests we established reliability database with narrower pitch what's more, we improve the First time yield and resolve the difficulties of processing by optimizing the structure and technology. That includes the size, pitch, height and verticality of copper pillar bump.
Starting Page	70
Ending Page	73
File Size	420988
Page Count	4
File Format	PDF
ISBN	9781479947072
DOI	10.1109/ICEPT.2014.6922598
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-08-12
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Copper Substrates Etching Films Conferences Electronics packaging Resins Organic substrate Copper pillar bump Modified Semi-Additive Process
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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