NDLI: Virtual prototyping of a Wafer Level Chip Scale Package: Underfill role in die cracking

Content Provider	IEEE Xplore Digital Library
Author	Barnat, S. Bellenger, S. Fremont, H. Gracia, A. Talbot, P.
Copyright Year	2009
Description	Author affiliation: NXP Semiconductors, Caen 14000, France (Barnat, S.; Bellenger, S.; Talbot, P.) \|\| Université Bordeaux I, Laboratoire IMS, CNRS UMR 5218, ENSEIRB, Talence 33405 cedex, France (Fremont, H.; Gracia, A.)
Abstract	With the increased complexity of SiP (system in package), Finite Element simulations take an important role in predicting the thermo-mechanical package reliability. Failures in flip chip packages such as die cracking and fatigue of solder bumps are specially the result of the mismatch in thermal expansion coefficients between die and the substrate. In some packages, we use an underfill to improve the reliability of the flip chip by reducing stress in the die and in bumps. But the choice of the underfill depends on the application. Using simulations allows us to better choose the right underfill. To perform this virtual prototyping, a methodology is followed and described. This paper highlights the effect of underfill on die cracking at Wafer Level Chip Scale Package (WLCSP) and exhibits ways to prevent this failure. The package analyzed is a WLCSP SiP composed by three active chips flipped on an Integrated Passive Die (IPD) and all assembled on a flex using lead-free solder bumps. Various kinds of underfill are tested in this assembly. The underfill used has a significant role in the fracture of the die.
Starting Page	1
Ending Page	6
File Size	10116326
Page Count	6
File Format	PDF
ISBN	9781424441600
DOI	10.1109/ESIME.2009.4938467
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-04-26
Publisher Place	The Netherlands
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Virtual prototyping Chip scale packaging Wafer scale integration Flip chip Assembly Finite element methods Predictive models Thermomechanical processes Fatigue Thermal expansion virtual prototyping Underfill die crack reliability CSP SiP
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Wafer level underfill - processing and reliability

Effect of underfill design parameters on die cracking in flip chip on flexible substrates

Assembly and reliability of flip chips with a nano-filled wafer level underfill

Effects of Underfill Materials and Thermal Cycling on Mechanical Reliability of Chip Scale Package

Experimental and numerical analyses of flip-chip attach reliability

Virtual Prototyping based Design Optimization of the Substrate, Leadframe, and Flip Chip Package Families with Low-k Technology

Improved thermal fatigue reliability for flip chip assemblies using redistribution techniques

3-D Structure Design and Reliability Analysis of Wafer Level Package With Stress Buffer Mechanism

Effect of underfill fillet configuration on flip chip package reliability

Virtual prototyping of a Wafer Level Chip Scale Package: Underfill role in die cracking

Similar Documents

Wafer level underfill - processing and reliability

Effect of underfill design parameters on die cracking in flip chip on flexible substrates

Assembly and reliability of flip chips with a nano-filled wafer level underfill

Effects of Underfill Materials and Thermal Cycling on Mechanical Reliability of Chip Scale Package

Experimental and numerical analyses of flip-chip attach reliability

Virtual Prototyping based Design Optimization of the Substrate, Leadframe, and Flip Chip Package Families with Low-k Technology

Improved thermal fatigue reliability for flip chip assemblies using redistribution techniques

3-D Structure Design and Reliability Analysis of Wafer Level Package With Stress Buffer Mechanism

Effect of underfill fillet configuration on flip chip package reliability

Virtual prototyping of a Wafer Level Chip Scale Package: Underfill role in die cracking