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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jibing Qiu Guihai Yan Xiaowei Li |
| Copyright Year | 2014 |
| Description | Author affiliation: State Key Lab. of Comput. Archit., Inst. of Comput. Technol., Beijing, China (Jibing Qiu; Guihai Yan; Xiaowei Li) |
| Abstract | The precision of on-chip delay sensors is degraded by temperature fluctuations, which hinders these sensors from applying to on-line fault predicting and DVFS. We present a novel path delay measuring technique which is immune to large temperature fluctuation. The delay reference are generated by gate biasing temperature compensation devices in which the pull-up and pull-down network are tuned to set the measurement circuit working in temperature insensitive point, thereby eliminating the precision degradation due to temperature variations. Video image scaling IP is used as experimental circuit to validate the effectiveness of the proposed technique. Experimental results show that within temperature range of -55°C to 125°C, the measurement error is reduced from 19.56% to 0.5%, compared with the techniques without temperature resilience. |
| Sponsorship | IEEE Comput. Soc. |
| Starting Page | 275 |
| Ending Page | 280 |
| File Size | 313624 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781479960309 |
| ISSN | 10817735 |
| DOI | 10.1109/ATS.2014.65 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-11-16 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Delays Temperature measurement Temperature sensors Delay lines Logic gates Inverters Semiconductor device measurement temperature resilience Critical path delay measurement temperature variation |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering |
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