NDLI: Holistic verification: Myth or magic bullet?

Content Provider	IEEE Xplore Digital Library
Author	Thaker, P.A.
Copyright Year	2009
Description	Author affiliation: Analog Devices Inc., Bangalore, India (Thaker, P.A.)
Abstract	Development of multi-million gate SoCs/ICs enabled by advances in submicron technology inherit verification complexity due to feature diversity on a single die and thus convergence of multiple design disciplines on one project with time-to-market pressures unchanged. For example, it is not uncommon for SoCs to integrate mixed-signal components, provide power-management features, contain instances of soft as well as hard $3^{rd}$ party IPs or large building blocks developed in-house and support compliance/compatibility requirements ranging from functional to electrical aspects for various standard-based protocols. Timely and high-confidence verification sign-off for such SoCs/ICs requires a multi-prong strategy defined in this paper as holistic verification. Holistic verification emphasizes a cocktail of verification methodologies designed to address specific verification challenges of a given SoC as well as advocates aspects of verification planning and design-for-verification techniques that aid verification efforts and enhance verification efficiency. Additionally, this paper describes details of verification challenges associated with mixed-signal integration and power management features of SoCs - two distinctly different design disciplines converging in one project and thus adding growing complexity to verification.
Starting Page	204
Ending Page	208
File Size	192014
Page Count	5
File Format	PDF
ISBN	9781605584973
ISSN	0738100X
DOI	10.1145/1629911.1629968
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-07-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Context modeling Design methodology Energy management System testing Time to market Protocols Project management Silicon Permission Convergence Power management Verification SoC Verification Emulation Mixed-signal Verification
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Holistic verification: myth or magic bullet?

A Holistic Approach to SoC Verification

Power Management Verification An Evolving Discipline

What's between simulation and formal verification?

Hardware/Software Method of Digital SoC Verification

Accelerated SOC Verification Using UVM Methodology for a Mixed- Signal Low Power Design

Study On a Mixed Verification Strategy for IP-Based SoC Design

A "design for verification" methodology

Using embedded infrastructure IP for SOC post-silicon verification

Holistic verification: Myth or magic bullet?

Similar Documents

Holistic verification: myth or magic bullet?

A Holistic Approach to SoC Verification

Power Management Verification  An Evolving Discipline

What's between simulation and formal verification?

Hardware/Software Method of Digital SoC Verification

Accelerated SOC Verification Using UVM Methodology for a Mixed- Signal Low Power Design

Study On a Mixed Verification Strategy for IP-Based SoC Design

A "design for verification" methodology

Using embedded infrastructure IP for SOC post-silicon verification

Holistic verification: Myth or magic bullet?

Power Management Verification An Evolving Discipline