NDLI: Handling don't-care conditions in high-level synthesis and application for reducing initialized registers

Content Provider	IEEE Xplore Digital Library
Author	Hong-Zu Chou Kai-Hui Chang Sy-Yen Kuo
Copyright Year	2009
Description	Author affiliation: Electrical Engineering Department, National Taiwan University, Taipei, Taiwan (Hong-Zu Chou; Sy-Yen Kuo) \|\| Avery Design Systems, Inc., Andover, MA, USA (Kai-Hui Chang)
Abstract	Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle such conditions accurately at the behavior and register transfer levels, which is problematic since the trend is to move toward high-level synthesis. In this work we propose innovative methods to handle such conditions accurately at high-level designs. In addition, we propose two novel algorithms based on our new methods to minimize the number of registers that need to be initialized at the architecture level, which can reduce the routing resources used by the reset signals and alleviate the routing problem. Our results show that we can identify 53% of the registers that can be uninitialized in a 5-stage pipelined processor within 5 minutes, demonstrating the effectiveness of our approach.
Starting Page	412
Ending Page	415
File Size	329437
Page Count	4
File Format	PDF
ISBN	9781605584973
ISSN	0738100X
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-07-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	High level synthesis Routing Distributed control Registers Design optimization Permission Logic design Optimization methods Algorithm design and analysis Heuristic algorithms Synthesis Don't-Care (DC) RTL symbolic simulation
Content Type	Text
Resource Type	Article

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