NDLI: Clock skew optimization via wiresizing for timing sign-off covering all process corners

Content Provider	IEEE Xplore Digital Library
Author	Onaissi, S. Heloue, K.R. Najm, F.N.
Copyright Year	2009
Description	Author affiliation: Dept. of ECE, Univ. of Toronto, Toronto, ON, Canada (Onaissi, S.; Heloue, K.R.; Najm, F.N.)
Abstract	Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, variability in clock networks is either handled early in the design flow by assigning margins to clock network delays, or at a later stage through post-processing steps that only focus on achieving minimal skew, without regard to functional block variability. In this work, we present a technique that alters clock network lines so that the circuit meets its timing constraints at all process corners. This is done near the end of the design flow while considering delay variability in both the clock network and the functional blocks. Our method operates at the physical level and provides designers with the required changes in clock network line widths and/or lengths. This can be formulated as a linear programming (LP) problem, and thus can be solved efficiently. Empirical results for a set of ISCAS-89 benchmark circuits show that our approach can considerably reduce the effect of process variations on circuit performance.
Starting Page	196
Ending Page	201
File Size	512146
Page Count	6
File Format	PDF
ISBN	9781605584973
ISSN	0738100X
DOI	10.1145/1629911.1629964
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-07-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Clocks Timing Circuit optimization Manufacturing processes Logic circuits Delay effects Linear programming Wire Hardware Integrated circuit reliability wiresizing Clock skew optimization variability sign-off parameterized timing analysis
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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