NDLI: NoC topology synthesis for supporting shutdown of voltage islands in SoCs

Content Provider	IEEE Xplore Digital Library
Author	Seiculescu, C. Murali, S. Benini, L. De Micheli, G.
Copyright Year	2009
Description	Author affiliation: LSI, EPFL, Lausanne, Switzerland (Seiculescu, C.; De Micheli, G.)
Abstract	In many systems on chips (SoCs), the cores are clustered in to voltage islands. When cores in an island are unused, the entire island can be shutdown to reduce the leakage power consumption. However, today, the interconnect architecture is a bottleneck in allowing the shutdown of the islands. In this paper, we present a synthesis approach to obtain customized application-specific networks on chips (NoCs) that can support the shutdown of voltage islands. Our results on realistic SoC benchmarks show that the resulting NoC designs only have a negligible overhead in SoC active power consumption (average of 3%) and area (average of 0.5%) to support the shutdown of islands. The shutdown support provided can lead to a significant leakage and hence total power savings.
Starting Page	822
Ending Page	825
File Size	417186
Page Count	4
File Format	PDF
ISBN	9781605584973
ISSN	0738100X
DOI	10.1145/1629911.1630121
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-07-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Network-on-a-chip Topology Voltage Energy consumption Switches Integrated circuit interconnections Routing System-on-a-chip Power system interconnection Network synthesis topology NoC voltage islands shutdown leakage power
Content Type	Text
Resource Type	Article

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