NDLI: Study On a Mixed Verification Strategy for IP-Based SoC Design

Content Provider	IEEE Xplore Digital Library
Author	Chen Wenwei Zhang Jinyi Li Jiao Ren Xiaojun Liu Jiwei
Copyright Year	2005
Description	Author affiliation: Microelectron. R & D Centre, Shanghai Univ. (Chen Wenwei)
Abstract	The demands for more powerful products and the huge capacity of today' s silicon technology move system-on-chip (SoC) designs from the leading-age to mainstream design practice. The one at the very top of the list of challenges to be solved for SoC design is verification. General agreement among many observers is that verification consumes at least 70 percent of whole design percent. SoC verification involves in multi-levels: IP level verification, chip level verification, and hardware/software (HW/SW) co-verification. The last one is the key point to the whole verification process, and some of EDA vendors have provided several EDA tools for HW/SW co-verification. In this paper, the author analyses the architecture of co-verification and the weakness of existing EDA tools, then presents a practical verification strategy based on FPGA, which is more flexible and convenient, and more efficient than traditional verification methods whose hardware and software verification are separate. An experimental result, VAD (video add data) SoC verification, is given as well finally
Starting Page	1
Ending Page	4
File Size	187816
Page Count	4
File Format	PDF
ISBN	0780392922
DOI	10.1109/HDP.2005.251451
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-06-27
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	System-on-a-chip Electronic design automation and methodology Hardware Silicon Application specific integrated circuits Testing Microelectronics Research and development Design engineering Power engineering and energy HW/SW co-verification SoC IP core Verification platfrom
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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