NDLI: Non-cycle-accurate Sequential Equivalence Checking

Content Provider	IEEE Xplore Digital Library
Author	Chauhan, P. Goyal, D. Hasteer, G. Mathur, A. Sharma, N.
Copyright Year	2009
Description	Author affiliation: Calypto Design Syst., Inc., Santa Clara, CA, USA (Chauhan, P.; Goyal, D.; Hasteer, G.; Mathur, A.; Sharma, N.)
Abstract	We present a novel technique for sequential equivalence checking (SEC) between non-cycle-accurate designs. The problem is routinely encountered in verifying the correctness of a system-level model versus an RTL design which has been derived from the former either manually or through high-level synthesis. The existing state-of-the-art in formal verification/SEC does not provide an efficient mechanism to perform such an equivalence check. Our technique reduces the SEC problem to a cycle-accurate equivalence-checking problem by constructing a pair of normalized cycle-accurate designs from the original designs, on which standard equivalence-checking techniques can then be deployed. We report the results of deploying our techniques on several industrial examples.
Starting Page	460
Ending Page	465
File Size	398122
Page Count	6
File Format	PDF
ISBN	9781605584973
ISSN	0738100X
DOI	10.1145/1629911.1630033
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-07-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	High level synthesis Algorithm design and analysis Formal verification Processor scheduling Concurrent computing Permission Machinery production industries Performance analysis Hardware Job shop scheduling High Level Synthesis Sequential Equivalence Checking Model Checking Formal Verification Unit Product Machine
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Non-cycle-accurate sequential equivalence checking

Industrial scale formal verification using concurrent GSTE

Scheduling and Binding Algorithms for High-Level Synthesis

An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis

Leveraging sequential equivalence checking to enable system-level to RTL flows

Symbolic model checking of process networks using interval diagram techniques

Predictive runtime verification of multi-processor SoCs in SystemC

Dynamic common sub-expression elimination during scheduling in high-level synthesis

A coevolutiouary genetic algorithm for job shop scheduling problems

Non-cycle-accurate Sequential Equivalence Checking

Similar Documents

Non-cycle-accurate sequential equivalence checking

Industrial scale formal verification using concurrent GSTE

Scheduling and Binding Algorithms for High-Level Synthesis

An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis

Leveraging sequential equivalence checking to enable system-level to RTL flows

Symbolic model checking of process networks using interval diagram techniques

Predictive runtime verification of multi-processor SoCs in SystemC

Dynamic common sub-expression elimination during scheduling in high-level synthesis

A coevolutiouary genetic algorithm for job shop scheduling problems

Non-cycle-accurate Sequential Equivalence Checking