NDLI: Evaluating design trade-offs in customizable processors

Content Provider	IEEE Xplore Digital Library
Author	Bordoloi, U.D. Huynh Phung Huynh Chakraborty, S. Mitra, T.
Copyright Year	2009
Description	Author affiliation: Verimag Labs., France (Bordoloi, U.D.)
Abstract	The short time-to-market window for embedded systems demands automation of design methodologies for customizable processors. Recent research advances in this direction have mostly focused on single criteria optimization, e.g., optimizing performance though custom instructions under pre-defined area constraint. From the designer's perspective, however, it would be more interesting if the conflicting trade-offs among multiple objectives (e.g., performance versus area) are exposed enabling an informed decision making. Unfortunately, identifying the optimal trade-off points turns out to be computationally intractable. In this paper, we present a polynomial-time approximation algorithm to systematically evaluate the design trade-offs. In particular, we explore performance-area trade-offs in the context of multi-tasking real-time embedded applications to be implemented on a customizable processor.
Starting Page	244
Ending Page	249
File Size	842765
Page Count	6
File Format	PDF
ISBN	9781605584973
ISSN	0738100X
DOI	10.1145/1629911.1629978
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-07-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Polynomials Approximation algorithms Embedded system Constraint optimization Algorithm design and analysis Process design Silicon Real time systems Design automation Permission Pareto-optimal curve ASIP Processor customization Multi-objective design space exploration
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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