NDLI: Untwist your brain - Efficient debugging and diagnosis of complex assertions

Content Provider	IEEE Xplore Digital Library
Author	Siegel, M. Maggiore, A. Pichler, C.
Copyright Year	2009
Description	Author affiliation: OneSpin Solutions, 1183 Bordeaux Drive, Suite 16, Sunnyvale, CA 94089, USA (Maggiore, A.) \|\| OneSpin Solutions, Theresienhoehe 12, 80339 Munich, Germany (Siegel, M.; Pichler, C.)
Abstract	Assertions are recognized in the industry to be a major improvement in functional RTL verification flows. Today's standard assertion languages, such as SVA [1] and PSL [2], are very expressive, capable of describing sophisticated temporal design behavior at different abstraction levels. Nevertheless, most assertion users stick to writing simple assertions because of the intricacy and effort required to debug complex assertions - one of the major bottlenecks in assertion based verification. We present debugging and diagnosis techniques that automatically identify those parts of an assertion that cause the assertion to fail for a given design and that provide additional automation to efficiently identify the root cause of the failure. These techniques enable major effort savings when working with complex assertions, allowing engineers to use the full capabilities of assertion languages. This enables further productivity and quality improvements in functional verification by lifting mainstream assertion usage to higher abstraction levels such as efficient capture and verification of high-level design features, operations, and transactions. Advanced debugging automation is key for this progress - solving a problem that many designers and verification engineers face in their daily work.
Starting Page	644
Ending Page	647
File Size	337434
Page Count	4
File Format	PDF
ISBN	9781605584973
ISSN	0738100X
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-07-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Debugging Algorithm design and analysis Design automation Formal verification Productivity Circuit simulation Permission Writing Design engineering Automatic testing SystemVerilog Assertions Functional Verification Assertions Root Cause Analysis Fault Localization
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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