NDLI: Dynamic thread and data mapping for NoC based CMPs

Content Provider	IEEE Xplore Digital Library
Author	Kandemir, M. Ozturk, O. Muralidhara, S.P.
Copyright Year	2009
Description	Author affiliation: Pennsylvania State Univ., University Park, PA, USA (Kandemir, M.; Muralidhara, S.P.)
Abstract	Thread mapping and data mapping are two important problems in the context of NoC (network-on-chip) based CMPs (chip multiprocessors). While a compiler can determine suitable mappings for data and threads, such static mappings may not work well for multithreaded applications that go through different execution phases during their execution, each phase with potentially different data access patterns than others. Instead, a dynamic mapping strategy, if its overheads can be kept low, may be a more promising option. In this work, we present dynamic (runtime) thread and data mappings for NoC based CMPs. The goal of these mappings is to reduce the distance between the location of the core that requests data and the core whose local memory contains that requested data. In our experiments, we evaluate our proposed thread mapping and data mapping in isolation as well as in an integrated manner.
Starting Page	852
Ending Page	857
File Size	425797
Page Count	6
File Format	PDF
ISBN	9781605584973
ISSN	0738100X
DOI	10.1145/1629911.1630129
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-07-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Yarn Network-on-a-chip Parallel processing Data mining Runtime Permission Application software Partitioning algorithms Computer languages Dynamic programming CMP Thread data dynamic mapping NoC
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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