NDLI: WCET-aware register allocation based on graph coloring

Content Provider	IEEE Xplore Digital Library
Author	Falk, H.
Copyright Year	2009
Description	Author affiliation: Comput. Sci. 12, Tech. Univ. Dortmund, Dortmund, Germany (Falk, H.)
Abstract	Current compilers lack precise timing models guiding their built-in optimizations. Hence, compilers apply ad-hoc heuristics during optimization to improve code quality. One of the most important optimizations is register allocation. Many compilers heuristically decide when and where to spill a register to memory, without having a clear understanding of the impact of such spill code on a program's run time. This paper extends a graph coloring register allocator such that it uses precise worst-case execution time (WCET) models. Using this WCET timing data, the compiler tries to avoid spill code generation along the critical path defining a program's WCET. To the best of our knowledge, this paper is the first one to present a WCET-aware register allocator. Our results underline the effectiveness of the proposed techniques. For a total of 46 realistic benchmarks, we reduced WCETs by 31.2% on average. Additionally, the runtimes of our WCET-aware register allocator still remain acceptable.
Starting Page	726
Ending Page	731
File Size	536056
Page Count	6
File Format	PDF
ISBN	9781605584973
ISSN	0738100X
DOI	10.1145/1629911.1630100
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-07-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Registers Optimizing compilers Program processors Design optimization Real time systems Timing Runtime Embedded system Permission Safety Register Allocation WCET
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Optimal static WCET-aware scratchpad allocation of program code

WCET-aware Register Allocation Based on Integer-Linear Programming

Tailoring graph-coloring register allocation for runtime compilation

WCET-aware register allocation based on graph coloring

Design of a WCET-Aware C Compiler

Improving WCET by optimizing worst-case paths

WCET-Aware Re-Scheduling Register Allocation for Real-Time Embedded Systems With Clustered VLIW Architecture

Whole program compilation for embedded software: the ADSL experiment

Combining Worst-Case Timing Models, Loop Unrolling, and Static Loop Analysis for WCET Minimization

WCET-aware register allocation based on graph coloring

Similar Documents

Optimal static WCET-aware scratchpad allocation of program code

WCET-aware Register Allocation Based on Integer-Linear Programming

Tailoring graph-coloring register allocation for runtime compilation

WCET-aware register allocation based on graph coloring

Design of a WCET-Aware C Compiler

Improving WCET by optimizing worst-case paths

WCET-Aware Re-Scheduling Register Allocation for Real-Time Embedded Systems With Clustered VLIW Architecture

Whole program compilation for embedded software: the ADSL experiment

Combining Worst-Case Timing Models, Loop Unrolling, and Static Loop Analysis for WCET Minimization

WCET-aware register allocation based on graph coloring