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Comparison Results on Fu and Register Counts Accurately Handle Don't-care Conditions in High-level Designs and Application for Reducing Initialized Registers Chou Et Al.: Accurately Handle Don't-care Conditions in High-level Designs and Application for Reducing Initialized Registers 647
| Content Provider | Semantic Scholar |
|---|---|
| Author | Cong, Junjie Jiang, Wenzhou Huang, C-Y Chen, Y-S. Cormen, H. Leiserson, Charles E. Rivest, Ronald L. Stein, Claire Srivastava, M. B. Potkonjak, Mary Chou, Hong-Zu Chang, Kai-Hui Bahar Chou, H. M. Chang, K-H. |
| Abstract | BIP Ours Inc (%) BIP Ours Inc (%) Bench N+ N * N+ N * N+ N * Reg Reg aircraft 38 40 38 40 0 0 159 159 0 chem 15 16 15 16 0 0 48 48 0 dir 8 7 8 7 0 0 72 72 0 feig dct 37 12 40 12 8 0 114 132 17 honda 7 6 7 7 0 1 7 24 24 0 mcm 12 9 13 9 8 0 38 40 5 pr 5 8 6 9 20 13 18 20 11 u5ml 16 17 16 17 0 0 60 60 0 wang 5 8 5 8 0 0 20 21 5 arai 6 3 6 3 0 0 14 19 36 lee 8 4 8 4 0 0 17 20 18 diffeq 2 2 2 3 0 5 0 7 7 0 fir11 1 2 1 2 0 0 11 11 0 cftmdl 15 16 16 16 7 0 34 41 21 cftb1st 12 6 14 6 17 0 52 58 12 fft 4 4 5 5 25 25 16 16 0 idct 10 9 11 9 10 0 39 39 0 matmul 16 32 16 32 0 0 48 48 0 wavelet 8 1 6 8 1 6 0 0 25 25 0 jacob 10 8 10 8 0 0 30 30 0 chendct 12 8 13 8 8 0 33 39 18 chenidct 15 12 15 12 0 0 39 40 3 kalman 2 2 3 2 50 0 8 9 13 lowpass 6 8 6 8 0 0 44 49 11 AVG 6 4 7 tion in percentage. As the table shows, our algorithm can reduce the multiplexer input by 33%, 29%, and 22% on average in comparison to LEA, BIP, and k-cof algorithm, respectively. In order to verify that reducing the number of multiplexer inputs leads to global interconnect minimization, we generated the layout of all benchmark designs using Cadence SOC Encounter, a widely used commercial EDA tool, and measured the actual total wirelength. Specifically, all binding results were first converted into Verilog register transfer level (RTL) description. The same place and routing flow was applied to all the RTL designs. The FUs were predesigned as hard macro-cells. The timing target of each benchmark design was kept constant. After circuit layouts were created, we used SOC Encounter to report the total wirelength of all interconnects … |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.kaihuichang.com/publication/tcad10.pdf |
| Alternate Webpage(s) | http://www.eecs.umich.edu/~changkh/publication/tcad10.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
