NDLI: Fast falsification based on symbolic bounded property checking

Content Provider	IEEE Xplore Digital Library
Author	Peranandam, P.M. Nalla, P.K. Ruf, J. Weiss, R.J. Kropf, T. Rosenstiel, W.
Copyright Year	2006
Description	Author affiliation: Tubingen Univ. (Peranandam, P.M.; Nalla, P.K.; Ruf, J.; Weiss, R.J.; Kropf, T.; Rosenstiel, W.)
Abstract	Symbolic property verification is an increasingly popular debugging method based on binary decision diagrams (BDDs). The lack of optimization of the state space search is often responsible for the excessive growth of the BDDs. In this paper, we present accelerated symbolic property verification by means of a new guiding technique that automatically finds the set of interesting variables by exploiting the property and the transition relation of a design. Our property based state space guiding can substantially speed up the verification process. The heuristic picks up the interesting state or the input variables automatically and utilizes them in guiding the state space traversal. This guiding approach is automatic, efficient and stable for fast falsification. Furthermore it does not degrade as much for full validation
Sponsorship	SiCda EDA Consortium IEEE Circuits & Syst. Soc. IEEE CASS/CANDE CANDE CEDA
Starting Page	1077
Ending Page	1082
File Size	3245587
Page Count	6
File Format	PDF
ISBN	1595933816
ISSN	0738100X
DOI	10.1109/DAC.2006.229400
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-07-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	State-space methods Data structures Boolean functions Partitioning algorithms Acceleration Proposals Algorithm design and analysis Formal verification Automatic control Input variables Guiding Verification Property Checking Fast Falsification
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Dynamic guiding of bounded property checking

Fast falsification based on symbolic bounded property checking

Evaluation of SAT-based Bounded Model Checking of ACTL Properties

Dynamic Guiding of Bounded Property Checking

SAT-based unbounded symbolic model checking

Symbolic model checking for sequential circuit verification

Overlap reduction in symbolic system traversal

Maximality-based symbolic model checking

Bounded Model Checking of Compositional Processes

Fast falsification based on symbolic bounded property checking

Similar Documents

Dynamic guiding of bounded property checking

Fast falsification based on symbolic bounded property checking

Evaluation of SAT-based Bounded Model Checking of ACTL Properties

Dynamic Guiding of Bounded Property Checking

SAT-based unbounded symbolic model checking

Symbolic model checking for sequential circuit verification

Overlap reduction in symbolic system traversal

Maximality-based symbolic model checking

Bounded Model Checking of Compositional Processes

Fast falsification based on symbolic bounded property checking