NDLI: Evaluation of SAT-based Bounded Model Checking of ACTL Properties

Content Provider	IEEE Xplore Digital Library
Author	Yanyan Xu Wei Chen Liang Xu Wenhui Zhang
Copyright Year	2007
Description	Author affiliation: Chinese Acad. of Sci., Beijing (Yanyan Xu; Wei Chen; Liang Xu; Wenhui Zhang)
Abstract	Bounded model checking (BMC) based on SAT has been introduced as a complementary method to BDD based symbolic model checking of LTL and ACTL properties in recent years. For general LTL and ACTL properties, BMC has traditionally aimed mainly at error detection, taking the advantage that error detection may only need to explore a small portion of the whole state space. Recently bounded model checking aiming at verification has also been proposed. The aim of this paper is to exploit the strength of BMC methods by combining different BMC approaches and compare it with the traditional BDD-based symbolic methods. We consider two bounded model checking methods, which are for error detection and verification of ACTL properties, respectively, and then combine them to a BMC algorithm. Based on this algorithm, we have implemented a tool named BMV (bounded model verifier), and carried out a number of experiments, and we have then compared BMV with Cadence SMV. The experimental results show that for certain types of problems, both for verification and error detection, BMV can perform much better than Cadence SMV in both time and memory consumption, and we believe that this is the first attempt to have an implementation of a method that combines practical error detection and verification of ACTL properties by SAT-based model checking.
Starting Page	339
Ending Page	348
File Size	450499
Page Count	10
File Format	PDF
ISBN	9780769528564
DOI	10.1109/TASE.2007.22
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-06-06
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer science Information science Boolean functions Minimization methods Laboratories Automatic logic units Data structures State-space methods Partitioning algorithms Formal verification
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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