NDLI: Circuit simulation based obstacle-aware Steiner routing

Content Provider	IEEE Xplore Digital Library
Author	Yiyu Shi Mesa, P. Hao Yu Lei He
Copyright Year	2006
Description	Author affiliation: Dept. of Electr. Eng., California Univ., Los Angeles, CA (Yiyu Shi; Mesa, P.; Hao Yu; Lei He)
Abstract	Steiner routing is a fundamental yet NP-hard problem, in VLSI design and other research fields. In this paper, we propose to model the routing graph by an RC network with routing terminals as input ports and Hanan nodes as output ports. We show that the faster an output reaches its peak, the higher the possibility for the correspondent Hanan node to be a Steiner point. Iteratively adding one or multiple selected Steiner points to build and improve Steiner trees leads to 1-cktSteiner and Blocked-cktSteiner (in short, B-cktSteiner) algorithms, respectively. When there are no routing obstacles, 1-cktSteiner obtains similar wirelength compared with the best existing algorithm FastSteiner. Both are less than 1% worse than the exact solution, but 1-cktSteiner is up to 11.3times faster than FastSteiner. Compared with the fastest existing heuristic FLUTE, B-cktSteiner has similar runtime but up to 1.9% shorter wirelength. Different from FastSteiner and FLUTE which are only applicable to non-obstacle cases, 1-cktSteiner and B-cktSteiner can be applied to routing with obstacles with minimal runtime increase. Compared with the best existing obstacle-avoiding algorithm An-OARS Man, 1-cktSteiner has similar runtime and reduces wirelength by 6.12%. and B-cktSteiner has an average speedup of 352times with a similar wirelength
Sponsorship	SiCda EDA Consortium IEEE Circuits & Syst. Soc. IEEE CASS/CANDE CANDE CEDA
Starting Page	385
Ending Page	388
File Size	1610462
Page Count	4
File Format	PDF
ISBN	1595933816
ISSN	0738100X
DOI	10.1109/DAC.2006.229212
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-07-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Circuit simulation Routing Runtime Iterative algorithms Steiner trees Very large scale integration Helium NP-hard problem Voltage Numerical models OARSMT Algorithms Design Performance Simulation RSMT
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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