NDLI: Standard cell library optimization for leakage reduction

Content Provider	IEEE Xplore Digital Library
Author	Shah, S. Gupta, P. Kahng, A.
Copyright Year	2006
Description	Author affiliation: Michigan Univ., Ann Arbor, MI (Shah, S.)
Abstract	Scaling device geometries have caused leakage-power consumption to be one of the major challenges of deep sub-micron design and a major source for parametric yield loss. We propose a library optimization approach involving generation of additional variants for each cell master, by biasing gate-lengths of devices. We employ transistor-level gate-length assignment to exploit asymmetries in standard cell circuit topology as well slack distribution of the design. The enhanced library is used by a power optimizer to reduce design leakage without violating any timing constraints. Such transistor-level optimization of cell libraries offers significantly better leakage-delay tradeoff than simple cell-level biasing (CLB) proposed previously. Experimental results on benchmarks show transistor-level biasing (TLB) can improve the CLB leakage optimization results by 8-17%. There is a corresponding improvement in design leakage distribution as well
Sponsorship	SiCda EDA Consortium IEEE Circuits & Syst. Soc. IEEE CASS/CANDE CANDE CEDA
Starting Page	983
Ending Page	986
File Size	1845889
Page Count	4
File Format	PDF
ISBN	1595933816
ISSN	0738100X
DOI	10.1109/DAC.2006.229423
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-07-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Libraries Design optimization Timing Delay Threshold voltage Design for manufacture MOS devices Character generation Algorithm design and analysis Circuits Leakage reduction Design Performance Gate-length biasing Library optimization
Content Type	Text
Resource Type	Article

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