NDLI: Leakage-aware intraprogram voltage scaling for embedded processors

Content Provider	IEEE Xplore Digital Library
Author	Po-Kuan Huang Ghiasi, S.
Copyright Year	2006
Description	Author affiliation: Dept. of Electr. & Comput. Eng., California Univ., Davis, CA (Po-Kuan Huang; Ghiasi, S.)
Abstract	With scaling of technology feature sizes, the share of leakage in total power consumption of digital systems continues to grow. Conventional dynamic voltage scaling (DVS) techniques fail to accurately address the impact of scaling on system power consumption and hence, are incapable of achieving energy efficient solutions. To overcome this problem, we utilize adaptive body biasing (ABB) to adjust transistors' threshold voltage at runtime. We develop a leakage-aware compilation methodology that targets embedded processors with both DVS and ABB capabilities. Our technique has the unique advantage of jointly optimizing active and leakage energy dissipation. Considering the delay and energy penalty of switching between operating modes of the processor and under deadline constraint, our compiler improves the energy consumption of the generated code by average of 13.07% and up to 30.26% at 90nm. While our technique's improvement in energy dissipation over conventional DVS is marginal (4.54%) at 130nm, the average improvement continues to grow to 7.8%, 15.94% and 29.56% for 90nm, 65nm and 45 technology nodes, respectively
Sponsorship	SiCda EDA Consortium IEEE Circuits & Syst. Soc. IEEE CASS/CANDE CANDE CEDA
Starting Page	364
Ending Page	369
File Size	4263396
Page Count	6
File Format	PDF
ISBN	1595933816
ISSN	0738100X
DOI	10.1109/DAC.2006.229301
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-07-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Energy consumption CMOS technology Voltage control Dynamic voltage scaling Frequency Threshold voltage Digital systems Runtime Delay Energy dissipation Performance Algorithms Management
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Power-Aware Compilation for Embedded Processors with Dynamic Voltage Scaling and Adaptive Body Biasing Capabilities

Leakage-aware intraprogram voltage scaling for embedded processors

Leakage aware dynamic voltage scaling for real-time embedded systems

Runtime architecture adaptation for energy management in embedded real-time systems

Overhead-conscious voltage selection for dynamic and leakage energy reduction of time-constrained systems

Keeping hot chips cool

Combined dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems

Optimal supply and threshold scaling for subthreshold CMOS circuits

Power-composition profile driven co-synthesis with power management selection for dynamic and leakage energy reduction

Leakage-aware intraprogram voltage scaling for embedded processors

Similar Documents

Power-Aware Compilation for Embedded Processors with Dynamic Voltage Scaling and Adaptive Body Biasing Capabilities

Leakage-aware intraprogram voltage scaling for embedded processors

Leakage aware dynamic voltage scaling for real-time embedded systems

Runtime architecture adaptation for energy management in embedded real-time systems

Overhead-conscious voltage selection for dynamic and leakage energy reduction of time-constrained systems

Keeping hot chips cool

Combined dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems

Optimal supply and threshold scaling for subthreshold CMOS circuits

Power-composition profile driven co-synthesis with power management selection for dynamic and leakage energy reduction

Leakage-aware intraprogram voltage scaling for embedded processors