NDLI: Scheduling-based test-case generation for verification of multimedia SoCs

Content Provider	IEEE Xplore Digital Library
Author	Amir Nahir Avi Ziv Emek, R. Tal Keidar Ronen, Nir
Copyright Year	2006
Description	Author affiliation: IBM Res. Lab., Haifa (Amir Nahir; Avi Ziv)
Abstract	Multimedia SoCs are characterized by a main controller that directs the activity of several cores, each of which is in charge of a stage in the processing of a media stream. The verification of these SoCs is a significant challenge due to time-to-market constraints and system complexity. We present a novel approach to system-level, random test case generation for multimedia SoCs, and a tool, called SoCVer, that implements this approach. We use the SoCs main controller point of view for controlling the flow of data in the SoC. Test case generation is done by allocating processing tasks to the various cores and determining which core processes which data item at what time. Solving these scheduling problems allows SoCVer to generate software for the SoCs main controller; this software coordinates and synchronizes the operations of all the cores on the chip without the need for the real operational software. We demonstrate the use of SoCVer using a DVD player SoC
Sponsorship	SiCda EDA Consortium IEEE Circuits & Syst. Soc. IEEE CASS/CANDE CANDE CEDA
Starting Page	348
Ending Page	351
File Size	3238025
Page Count	4
File Format	PDF
ISBN	1595933816
ISSN	0738100X
DOI	10.1109/DAC.2006.229284
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-07-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Streaming media System testing Control systems System-on-a-chip Software testing Multimedia systems Software tools DVD Hardware Microelectronics Test Generation Verification Functional Verification System on a Chip
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Scheduling-based test-case generation for verification of multimedia SoCs

N.: Scheduling-based test-case generation for verification of multimedia SoCs

Modeling IP responses in test case generation for systems-on-chip verification

A generic hardware / software communication middleware for streaming applications on shared memory multi processor systems-on-chip

Hardware/Software Based Hierarchical Self Test for SoCs

High-level test generation for hardware testing and software validation

RTL-based functional test generation for high defects coverage in digital SOCs

On-line test and monitoring of multi-processor SoCs: A software-based approach

Definition of a systematic method for the generation of software test programs allowing the functional verification of system on chip (SoC)

Scheduling-based test-case generation for verification of multimedia SoCs

Similar Documents

Scheduling-based test-case generation for verification of multimedia SoCs

N.: Scheduling-based test-case generation for verification of multimedia SoCs

Modeling IP responses in test case generation for systems-on-chip verification

A generic hardware / software communication middleware for streaming applications on shared memory multi processor systems-on-chip

Hardware/Software Based Hierarchical Self Test for SoCs

High-level test generation for hardware testing and software validation

RTL-based functional test generation for high defects coverage in digital SOCs

On-line test and monitoring of multi-processor SoCs: A software-based approach

Definition of a systematic method for the generation of software test programs allowing the functional verification of system on chip (SoC)

Scheduling-based test-case generation for verification of multimedia SoCs