NDLI: Use of C/C++ models for architecture exploration and verification of DSPs

Content Provider	IEEE Xplore Digital Library
Author	Brier, D. Mitra, R.S.
Copyright Year	2006
Description	Author affiliation: Texas Instruments Inc., Dallas, TX (Brier, D.; Mitra, R.S.)
Abstract	Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural trade-offs that must be made for a practical implementation. The same models can be reused during the verification of the RTL subsequently developed, provided that various "hooks" which are desirable during the verification process are considered while creating these high level models. In addition, consideration must be given to the qualitative content of these high level models to permit an optimal verification flow allowing for compromise between features of the model and the completeness of the verification. Thus, high quality design and verification are achieved by the use of valid models and the valid use of models. In this paper, we describe our approach and show examples from a typical image processing application
Sponsorship	SiCda EDA Consortium IEEE Circuits & Syst. Soc. IEEE CASS/CANDE CANDE CEDA
Starting Page	79
Ending Page	84
File Size	3521532
Page Count	6
File Format	PDF
ISBN	1595933816
ISSN	0738100X
DOI	10.1109/DAC.2006.229169
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-07-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Digital signal processing Algorithm design and analysis Signal processing algorithms Instruments Image processing Documentation Pipelines Signal processing Logic design Signal design RTL Algorithms Design Languages Verification C/C++ Simulation Formal
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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