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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chen-Hsing Wang Chih-Yen Lo Min-Shenq Lee Jen-Chieh Yeh Chih-Tsun Huang Cheng-Wen Wu Shi-Yu Huang |
| Copyright Year | 2006 |
| Description | Author affiliation: Dept. of Elec. Eng., NTHU, Hsinchu (Chen-Hsing Wang; Chih-Yen Lo; Min-Shenq Lee; Jen-Chieh Yeh; Chih-Tsun Huang; Cheng-Wen Wu; Shi-Yu Huang) |
| Abstract | In this paper we present a generic network security processor (NSP) design suitable for a wide range of security related protocols in wired or wireless network applications. Following the platform-based design methodology, we develop four specific platforms, i.e., architecture platform, EDA platform, design-for-testability (DFT) platform, and prototyping platform, for our NSP design. With these platforms, design of the NSP chip becomes more efficient and systematic. A prototype chip of the NSP has been implemented and fabricated with a 0.18 mum CMOS technology. The chip area is 5 mm times 5 mm (with 1M gates approximately), including I/O pads. The operating clock rate is 80 MHz. The best performance of the crypto-engines is 1.025 Gbps for AES, 1.652 Mbps for RSA, 125.9/157.65 Mbps for HMAC-SHA1/MD5, and 2.56 Gbps for random number generator. Comparison result shows that our NSP is efficient in terms of performance, flexibility and scalability |
| Sponsorship | SiCda EDA Consortium IEEE Circuits & Syst. Soc. IEEE CASS/CANDE CANDE CEDA |
| Starting Page | 490 |
| Ending Page | 495 |
| File Size | 2536205 |
| Page Count | 6 |
| File Format | |
| ISBN | 1595933816 |
| ISSN | 0738100X |
| DOI | 10.1109/DAC.2006.229266 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-07-24 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Association for Computing Machinery, Inc. (ACM) |
| Subject Keyword | Process design Testing Prototypes CMOS technology Wireless application protocol Wireless networks Design methodology Electronic design automation and methodology Design for testability Clocks AMBA Design Security AES RSA HMAC-MD5 HMAC-SHA1 RNG |
| Content Type | Text |
| Resource Type | Article |
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