NDLI: A multi-port current source model for multiple-input switching effects in CMOS library cells

Content Provider	IEEE Xplore Digital Library
Author	Amin, C. Kashyap, C. Menezes, N. Killpack, K. Chiprout, E.
Copyright Year	2006
Description	Author affiliation: Strategic CAD Labs., Intel Corp., Hillsboro, OR (Amin, C.; Kashyap, C.; Menezes, N.; Killpack, K.; Chiprout, E.)
Abstract	The problem of multiple-input switching (MIS) has been mostly ignored by the timing CAD community. Not modeling MIS for timing can result in as much as 100% error in stage delay and slew calculation. The impact is especially severe on stages immediately after a bank of flops, where the inputs have a high probability of arriving simultaneously. Other problems such as modeling of interconnect loads, complex (nonlinear/nonmonotonic) input waveforms, power-droop impact on cell delay, nonlinear input capacitances, delay variations due to cross-capacitance, etc. are also known sources of error. In this paper, we introduce the multi-port current source model (MCSM). MCSM can efficiently handle an arbitrary number of simultaneously switching inputs, including single-input switching (SIS). Moreover, MCSM is comprehensive in that other modeling problems associated with delay and noise computation are elegantly covered. We demonstrate the applicability of MCSM on a large 65 nm industrial test-case. For cells experiencing MIS, the model yields delay and slew-rate errors within plusmn5% for 88.3% and 93.0% of the cases, respectively. We also present data that show that MCSM is an effective receiver model which captures active loading effects without incurring significant additional error. MCSM makes combined cell-level timing, noise, and power analysis a possibility
Sponsorship	SiCda EDA Consortium IEEE Circuits & Syst. Soc. IEEE CASS/CANDE CANDE CEDA
Starting Page	247
Ending Page	252
File Size	5824244
Page Count	6
File Format	PDF
ISBN	1595933816
ISSN	0738100X
DOI	10.1109/DAC.2006.229209
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-07-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Semiconductor device modeling Libraries Capacitance Timing Propagation delay Voltage Load modeling CMOS technology Delay effects Testing MCSM Performance Verification Design multiple input switching current source model timing analysis cell library characterization cell model
Content Type	Text
Resource Type	Article

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