NDLI: A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates

Content Provider	IEEE Xplore Digital Library
Author	Dadgour, H.F. Joshi, R.V. Banerjee, K.
Copyright Year	2006
Description	Author affiliation: Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA (Dadgour, H.F.)
Abstract	Substantial increase in leakage current and threshold voltage fluctuations are making design of robust wide fan-in dynamic gates a challenging task. Traditionally, a PMOS keeper transistor has been employed to compensate for leakage current of pull down (NMOS) network. However, to maintain acceptable noise margin level in sub-100 nm technologies, large PMOS is necessary, which results in substantial contention (during pull down) and severe loss of performance. In this paper, a novel keeper architecture is proposed which is capable of significantly reducing the contention and improving the performance and power consumption. Using circuit simulations, superior characteristics of the proposed keeper is demonstrated in comparison to those of the traditional as well as state-of-the-art keepers. It is shown that for an 8-input OR gate, in presence of 15% $V_{th}$ fluctuations, the proposed architecture can lead to 20%, 15%, and more than 40% reduction in power consumption, mean delay, and standard deviation of delay, respectively, when compared to traditional keeper circuit
Sponsorship	SiCda EDA Consortium IEEE Circuits & Syst. Soc. IEEE CASS/CANDE CANDE CEDA
Starting Page	977
Ending Page	982
File Size	3947418
Page Count	6
File Format	PDF
ISBN	1595933816
ISSN	0738100X
DOI	10.1109/DAC.2006.229422
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-07-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Leakage current Fluctuations Energy consumption Delay Threshold voltage Noise robustness MOS devices Circuit noise Noise level Performance loss VLSI Performance Design Reliability Dynamic gates process variation keeper design low-power design reliability robustness
Content Type	Text
Resource Type	Article

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