NDLI: Leakage optimization using transistor-level dual threshold voltage cell library

Content Provider	IEEE Xplore Digital Library
Author	Nagarajan, C.S. Lin Yuan Gang Qu Stamps, B.G.
Copyright Year	2009
Description	Author affiliation: University of Maryland, College Park, USA (Gang Qu) \|\| Cisco Systems Inc., San Jose, CA, USA (Nagarajan, C.S.) \|\| Synopsys, Inc., Mountain View, CA, USA (Lin Yuan) \|\| Atmel Corp., Columbia, MD, USA (Stamps, B.G.)
Abstract	Recently, a transistor level dual-Vth technique has been proposed, where transistors within the same cell are allowed to have different Vth to form the so-call mixed Vth (MVT) cell. However, it is impractical to build a full MVT cell library and include it in the standard dual Vth design flow. To make this practical, current approach adds another design phase after technology mapping to replace high leakage cells with their low leakage MVT variants. We propose a method to seamlessly and effectively integrate transistor-level dual Vth technology into existing low power design flow. This paper reports our successful experience in applying this method to optimize leakage under timing constraints in an industrial design environment. For demonstration purpose, we build an MVT library based on only 15 cells in a standard library that contains 590 cells. On 11 ISCAS benchmarks and three industrial designs, this MVT library optimizes 27% of the design. Yet it gives an average of 9% and up to 25% leakage saving over the state-of-art gate level dual Vth design with a full size high Vth library.
Starting Page	62
Ending Page	67
File Size	186377
Page Count	6
File Format	PDF
ISBN	9781424429523
DOI	10.1109/ISQED.2009.4810270
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-03-16
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Threshold voltage Libraries Circuits Delay Timing CMOS technology Constraint optimization Design optimization Batteries Costs transistor-level dual-Vth low power cell library leakage
Content Type	Text
Resource Type	Article

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