NDLI: Keeping hot chips cool

Content Provider	IEEE Xplore Digital Library
Author	Puri, R. Stok, L. Bhattacharya, S.
Copyright Year	2005
Description	Author affiliation: IBM T. J. Watson Res. Center, Yorktown Hts, NY, USA (Puri, R.)
Abstract	With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper outline practical techniques that are used to reduce both leakage as well as active power in a standard-cell library based high-performance design flow. We discuss the design and cost issues for using different power saving techniques such as: power gating to reduce leakage, multiple and hybrid threshold libraries for leakage reduction and multiple supply voltage based design. In addition techniques to reduce clock tree power are presented as power consumed in clocks accounts for a significant portion of total chip power. Practical aspects of implementing these techniques is also discussed.
Sponsorship	acm Special Interest Group on design automation (SIGda) EDA Consortium IEEE CASS/CANDE IEEE Circuits & Syst. Soc
Starting Page	285
Ending Page	288
File Size	720366
Page Count	4
File Format	PDF
ISBN	1595930582
DOI	10.1109/DAC.2005.193818
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-06-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Clocks Power dissipation Libraries Threshold voltage Runtime Voltage control Frequency CMOS technology Gate leakage Energy consumption
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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