NDLI: Fabrication of anodically bonded capacitive micromachined ultrasonic transducers with vacuum-sealed cavities

Content Provider	IEEE Xplore Digital Library
Author	Yamaner, F.Y. Xiao Zhang Oralkan, O.
Copyright Year	2014
Description	Author affiliation: Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA (Yamaner, F.Y.; Xiao Zhang; Oralkan, O.)
Abstract	Capacitive micromachined ultrasonic transducers (CMUTs) have demonstrated great promise for next-generation ultrasound technology. Wafer-bonding technology particularly simplifies the fabrication of CMUTs by eliminating the requirement for a sacrificial layer and increases control over device parameters. Anodic bonding has many advantages over other bonding methods such as low temperature compatibility, high bond strength, high tolerance to particle contamination and surface roughness, and cost savings. Furthermore, the glass substrates lower the parasitic capacitance and improve reliability. The major drawback is the trapped gas inside the cavities, which occurs during bonding. Earlier CMUT fabrication efforts using anodic bonding failed to demonstrate a vacuum-sealed cavity. In this study, we developed a fabrication scheme to overcome this issue and demonstrated vacuum-backed CMUTs using anodic bonding. This new approach also simplifies the overall fabrication process for CMUTs. We demonstrated a CMUT fabrication process with three lithography steps. A vibrating plate is formed by bonding the device layer of a silicon-on-insulator (SOI) wafer on top of submicron cavities defined on a borosilicate glass wafer. The cavities and the bottom electrodes are created on the borosilicate glass wafer with a single lithography step. The recessed bottom metal layer over the glass surface allows bonding the plate directly on glass posts and therefore helps reduce the parasitic capacitance and improve the breakdown reliability. A surface roughness of 0.8 nm is achieved in the cavity using wet chemical etching. A 200-nm PECVD silicon nitride layer deposited on the 2 μm device layer of the SOI wafer prior to bonding serves as the insulation layer to prevent shorting after pull-in. The trapped gas inside the cavities is evacuated after anodic bonding by reactive ion etching. The 120-nm cavities are then sealed with PECVD silicon nitride. We measured the atmospheric deflection of the plates after fabrication, which proves the vacuum inside the cavities. Impedance and hydrophone measurements were performed both in conventional (2.8 MHz) and collapse (7.2 MHz) modes. Bonding on posts with widths as small as 2 μm was successfully demonstrated using anodic bonding which is difficult to achieve with other wafer bonding methods.
Starting Page	604
Ending Page	607
File Size	2351502
Page Count	4
File Format	PDF
e-ISBN	9781479970490
DOI	10.1109/ULTSYM.2014.0148
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-09-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Bonding Cavity resonators Substrates Metals Glass Surface treatment
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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