NDLI: FinFET Logic Circuit Optimization with Different FinFET Styles: Lower Power Possible at Higher Supply Voltage

Content Provider	IEEE Xplore Digital Library
Author	Chaudhuri, S. Jha, N.K.
Copyright Year	2014
Description	Author affiliation: Dept. of Electr. Eng., Princeton Univ., Princeton, NJ, USA (Chaudhuri, S.; Jha, N.K.)
Abstract	Recently, FinFETs have attracted a lot of attention as a promising alternative to planar transistors, owing to their superior performance, lower leakage, and better tolerance of process variations. FinFETs come in different styles, among which shorted-gate (SG) and asymmetric gate-work function shorted-gate (ASG) are two of the most important ones. SG FinFET based standard cells are the fastest among all styles. However, ASG FinFET based standard cells have two orders of magnitude lower leakage. For cells of the same size, they have the same layout and, hence, the same area. We present a delay-constrained power optimization methodology in which the negligible amount of leakage power consumed by ASG cells plays a pivotal role. We use a higher supply voltage $(V_{DD})$ to reduce the delay of ASG logic circuits so that they become delay-competitive with SG logic circuits. This does increase the dynamic power consumption. However, the reduction in leakage power is so drastic that total power still goes down. The overall area may increase. Thus, a higher $V_{DD}$ enables a power- area tradeoff under a delay constraint. What is unusual about this scenario is that a higher $V_{DD}$ leads to lower total power under the same delay. We also evaluate hybrid FinFET logic circuits that contain a mix of SG and ASG cells operating at the same $V_{DD}.$ They yield other interesting points in the area- delay-power space. The advantage of our methodology is more pronounced at higher temperatures since leakage becomes a greater fraction of total power at higher temperatures (dynamic power barely increases with temperature in FinFET circuits whereas leakage power grows exponentially). For example, at 373K, when we compare SG FinFET circuits operating at 0.9V to ASG FinFET circuits operating at 1.0V, the latter consume, on an average, 47.0% less total power at the expense of a 6.9% area increase. When we compare SG FinFET circuits operating at 0.9V with hybrid circuits, which contain a mix of SG and ASG standard cells all operating at 0.9V, the latter consume, on an average, 31.7% less total power at the expense of a 10.8% area increase. Since the two approaches often complement each other, if the better of the two results is chosen, then at 373K, the power reduction is 50.0%, however, at the expense of a 9.9% area increase.
Sponsorship	IEEE Comput. Soc.
Starting Page	476
Ending Page	482
File Size	210139
Page Count	7
File Format	PDF
ISBN	9781479925131
ISSN	10639667
DOI	10.1109/VLSID.2014.89
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-05
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	FinFETs Delays Logic gates Benchmark testing Logic circuits Standards Optimization power optimization asymmetric gate-workfunction leakage power
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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