NDLI: A Novel Low Power Error Detection Logic for Inexact Leading Zero Anticipator in Floating Point Units

Content Provider	IEEE Xplore Digital Library
Author	Reddy, B.N.K. Sekhar, M.C. Veeramachaneni, S. Srinivas, M.B.
Copyright Year	2014
Description	Author affiliation: Dept. of Electr. Eng., Birla Inst. of Technol. & Sci. - Pilani, Hyderabad, India (Reddy, B.N.K.; Sekhar, M.C.; Veeramachaneni, S.; Srinivas, M.B.)
Abstract	In floating point addition unit, adder and normalization decides the critical path delay. By predicting the shift amount prior to the adder's output the delay introduced by the normalization can be reduced. This prediction is done using a technique called Leading Zero Anticipator (LZA). LZA algorithms are divided into exact and inexact categories. Most of the existing algorithms are inexact in nature which predicts the shift amount with a possible error of 1 bit. So, these inexact LZA algorithms need an error detection circuit. This paper proposes an error detection logic implemented in parallel with adder and using a part hardware of LZA resulting in reduction of both area and power consumption by 35%-39% and 44%-48% respectively when compared with that of general LZA and error detection circuit.
Sponsorship	IEEE Comput. Soc.
Starting Page	128
Ending Page	132
File Size	822491
Page Count	5
File Format	PDF
ISBN	9781479925131
ISSN	10639667
DOI	10.1109/VLSID.2014.29
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-05
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Adders Error correction Prediction algorithms Hardware Power demand Simulation Digital arithmetic Normalization Floating Point Addition Leading Zero Anticipator
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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