NDLI: Performance and Power Benefits of Sharing Execution Units between a High Performance Core and a Low Power Core

Content Provider	IEEE Xplore Digital Library
Author	Rodrigues, R. Koren, I. Kundu, S.
Copyright Year	2014
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Massachusetts, Amherst, MA, USA (Rodrigues, R.; Koren, I.; Kundu, S.)
Abstract	Several studies and real world designs have advocated the sharing of large execution units between pairs of cores in Symmetric Multicore Processors (SMP) for area and power savings. Such sharing was shown to have negligible impact on performance. Recently, a number of Asymmetric Multicore Processor (AMP) designs have become available. The objective of this paper is to investigate whether sharing of resources across AMPs offers similar benefits. Our study shows that while the area and the power savings remain similar, the performance of the smaller core in the AMP can improve significantly making sharing even more attractive for AMPs. Simulation results indicate that for certain workloads, the performance of the small core may improve by as much as 54% by sharing certain large execution resources of the big core, while affecting the performance of the big core by only ~4%, resulting in an overall gain in system performance of 20%. The corresponding improvement in aggregate performance/Watt is 12% while the area savings is about 7%.
Sponsorship	IEEE Comput. Soc.
Starting Page	204
Ending Page	209
File Size	904399
Page Count	6
File Format	PDF
ISBN	9781479925131
ISSN	10639667
DOI	10.1109/VLSID.2014.42
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-05
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Resource management Multicore processing Hardware Art Out of order Sensitivity performance/ Watt Asymmetric Multicore Processor (AMP) Symmetric Multicore Processor (SMP) resource sharing performance
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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