NDLI: Circuit for Reversible Quantum Multiplier Based on Binary Tree Optimizing Ancilla and Garbage Bits

Content Provider	IEEE Xplore Digital Library
Author	Kotiyal, S. Thapliyal, H. Ranganathan, N.
Copyright Year	2014
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA (Kotiyal, S.; Thapliyal, H.; Ranganathan, N.)
Abstract	Reversible logic has emerged as a promising computing paradigm having applications in quantum computing, optical computing, dissipation less computing and low power computing etc. In reversible logic there exists a one to one mapping between the input and output vectors. Reversible circuits require constant ancilla inputs for reconfiguration of gate functions and garbage outputs that help in keeping reversibility. Quantum circuits of many qubits are extremely difficult to realize thus reduction in the number of ancilla inputs and the garbage outputs is the primary goal of optimization. In existing literature researchers have proposed several designs of reversible quantum multipliers based on reversible full adders and reversible half adders. The use of reversible full adders and the half adders for the addition of partial products increases the overhead in terms of number of ancilla inputs and number of garbage outputs. This paper presents a binary tree based design methodology for a NxN reversible quantum multiplier. The proposed binary tree based design methodology for NxN reversible quantum multiplier performs the addition of partial products in parallel using the reversible ripple quantum adders with no garbage output and ancilla bit, thereby minimizing the number of ancilla and garbage bits used in the design. The proposed design methodology shows the improvement of 17.86% to 60.34% in terms of ancilla inputs; and 21.43% to 52.17% in terms of garbage outputs compared to all the existing reversible quantum multiplier designs.
Sponsorship	IEEE Comput. Soc.
Starting Page	545
Ending Page	550
File Size	283582
Page Count	6
File Format	PDF
ISBN	9781479925131
ISSN	10639667
DOI	10.1109/VLSID.2014.101
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-05
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Adders Binary trees Design methodology Quantum computing Optimization Quantum dots Quantum ALU Quantum Computing Quantum Multiplier
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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