NDLI: Pre-mapping Algorithm for Heterogeneous MPSoCs

Content Provider	IEEE Xplore Digital Library
Author	Marcon, C. Webber, T. Poehls, L.B. Pinotti, I.K.
Copyright Year	2014
Description	Author affiliation: Pontificia Univ. Catolica do Rio Grande do Sul, Porto Alegre, Brazil (Marcon, C.; Webber, T.; Poehls, L.B.; Pinotti, I.K.)
Abstract	A Multiprocessor System-on-Chip (MPSoC) composed of different types of processors is known as heterogeneous MPSoC. This kind of MPSoC based on Network-on-Chip (NoC) is a promising target architecture to fulfill requirements of high processing and communicating rate, enabling the execution of several tasks at the same time. Among the challenges in current heterogeneous MPSoC design is the partitioning of application tasks aiming for the energy saving and for a fair load balance. This work's contribution is twofold: (i) a partitioning algorithm is developed, and (ii) the evaluation of using partitioning as a pre-mapping task is explored. This work analyzes and compares stochastic and new heuristic partitioning algorithms for obtaining low energy consumption and for load balance when applied to tasks partitioning onto heterogeneous MPSoC. In addition, simulated results indicate that the static partitioning technique could be applied to application tasks before mapping activities in order to improve the quality of the static or dynamic mapping design and also to minimize the processing time.
Sponsorship	IEEE Comput. Soc.
Starting Page	252
Ending Page	257
File Size	522428
Page Count	6
File Format	PDF
ISBN	9781479925131
ISSN	10639667
DOI	10.1109/VLSID.2014.50
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-05
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Program processors Partitioning algorithms Energy consumption Tiles Algorithm design and analysis Heuristic algorithms Computer architecture heterogeneous MPSoC partitioning mapping
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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