NDLI: Scalable Low Power FFT/IFFT Architecture with Dynamic Bit Width Configurability

Content Provider	IEEE Xplore Digital Library
Author	Rangachari, S. Balakrishnan, J. Chandrachoodan, N.
Copyright Year	2014
Description	Author affiliation: Texas Instrum. India Pvt Ltd., Bangalore, India (Rangachari, S.; Balakrishnan, J.) \|\| Dept. of Electr. Eng., IITM, Chennai, India (Chandrachoodan, N.)
Abstract	In this paper, we present a novel architecture for a shared FFT/IFFT especially for OFDM transceiver applications, that can be dynamically configured to optimize the power consumption based on the operating scenario. This exploits the fact that the bit width needed to meet the required packet error rate varies across different operating scenarios while the hardware is designed for the worst case operating scenario. We propose an architecture with control signals that can be dynamically configured to reduce the average toggle activity to match that required for the specific operating scenario. We also exploit the fact that in the case of a transmit operation, the input signal comes from a known set of constellation points that may require fewer bits to represent without losing any information. These architecture modifications can be configured dynamically on a symbol-to-symbol basis based on several parameters, namely the modulation mode, input signal SNR, etc., and can be applied to most of the well known FFT architecture choices such as decimation-in-time, decimation-in-frequency with different base radix based on single-path delay feedback, multi-path delay commutator etc. The power consumption of the proposed architecture is compared with the traditional architecture in both transmit and receive modes of operation for a 64 point FFT/IFFT using pre-layout net list simulations on a 45nm library.
Sponsorship	IEEE Comput. Soc.
Starting Page	359
Ending Page	364
File Size	249741
Page Count	6
File Format	PDF
ISBN	9781479925131
ISSN	10639667
DOI	10.1109/VLSID.2014.68
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-05
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Power demand Shift registers Binary phase shift keying Wireless LAN Dynamic Configuration FFT IFFT OFDM
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in