NDLI: Hardware Implementation of Real-Time, High Performance, RCE-NN Based Face Recognition System

Content Provider	IEEE Xplore Digital Library
Author	Sardar, S. Babu, K.A.
Copyright Year	2014
Description	Author affiliation: Defence R&D Organ., New Delhi, India (Sardar, S.; Babu, K.A.)
Abstract	Hardware implementation of a real-time, highly accurate face recognition system (FRS) is proposed in this correspondence. Face images are acquired from a CMOS sensor camera connected to Field Programmable Gate Array (FPGA) based reconfigurable hardware board using Cam Link interface. We used contrast limited adaptive histogram equalization (CLAHE) for image contrast enhancement, discrete wavelet transform (DWT) to remove variable illumination & select appropriate subband and principal component analysis (PCA) with 35 principal components which is optimized for performance and speed. Finally, Restricted Coulomb Energy (RCE) based neural network (NN) classifier is used for face recognition. We have implemented the RCE based NN in FPGA and thus utilized the inherent parallelism effectively which is not possible with NN software implementation. The performance of our implementation is superior than face recognition software and hardware implementations, which are targeted to achieve higher recognition accuracy at faster rate using minimum computational resources. Our system recognizes a single image in real-time i.e. within 18 ms corresponding to 37 frames per second image capture. We have verified our proposed system with multiple standard face databases as well as using our own face data repository.
Sponsorship	IEEE Comput. Soc.
Starting Page	174
Ending Page	179
File Size	604047
Page Count	6
File Format	PDF
ISBN	9781479925131
ISSN	10639667
DOI	10.1109/VLSID.2014.37
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-05
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Face recognition Face Hardware Principal component analysis Neurons Histograms NN FRS CMOS FPGA CamLink CLAHE DWT PCA RCE
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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