NDLI: Obstacle Avoiding Rectilinear Clock Tree Construction with Skew Minimization

Content Provider	IEEE Xplore Digital Library
Author	Saha, P.P. Samanta, T.
Copyright Year	2014
Description	Author affiliation: MCKV Inst. of Eng., Liluah, India (Saha, P.P.) \|\| Bengal Eng. & Sci. Univ., Shibpur, India (Samanta, T.)
Abstract	Clock skew minimization plays an important role in VLSI interconnect design to assure enhanced synchronous performance of a chip. In this paper, we propose an Obstacle avoiding Rectilinear Clock tree construction algorithm navigating prioritized critical sink routing approach. Our proposed algorithm mostly focuses on delay equalization at all the sink terminals from the source, avoiding obstacle edges. The proposed method is maneuvered as follows. (1) Initially, the entire layout is divided into smaller rectangular or square sub zones, called tiles, containing subset of sink terminals. (2) Next, center of masses (CMs) of the tiles are computed based on arithmetic mean of the sink terminals associated with the tiles. Priority is assigned to the CMs based on Euclidean distance of the CMs from the source terminal. All the CMs are routed from the source to equalize delay of reaching signal to them, based on Elmore delay model. (3) Finally, a local delay balanced sub-tree is constructed in each tile, to equate delay from CM to the sink terminals, following Elmore delay structure. Elmore delay formula is adopted to calculate delay of a routing path, considering the resistive (R) and capacitive (C) effects of a wire. Proposed algorithm is run on some recent benchmark suits, and experimental results are quite encouraging.
Sponsorship	IEEE Comput. Soc.
Starting Page	387
Ending Page	392
File Size	227752
Page Count	6
File Format	PDF
ISBN	9781479925131
ISSN	10639667
DOI	10.1109/VLSID.2014.73
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-05
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Delays Routing Tiles Minimization Algorithm design and analysis Benchmark testing Clock Skew Minimization Clock Tree Elmore Delay Obstacle Obstacle Avoiding Rectilinear Clock Tree Construction
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

An algorithm for obstacle-avoiding clock routing tree construction with multiple TSVs on a 3D IC

Rectilinear Steiner Clock Tree Routing Technique with Buffer Insertion in Presence of Obstacles

Clock Tree Skew Minimization with Structured Routing

Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion

Post-layout OPE-predicted redundant wire insertion for clock skew minimization

Critical-Trunk-Based Obstacle-Avoiding Rectilinear Steiner Tree Routings and Buffer Insertion for Delay and Slack Optimization

Bounded-Skew Clock and Steiner Routing Under Elmore Delay (1995)

Bounded-Skew Clock and Steiner Routing Under Elmore Delay (1995)

Critical-trunk based obstacle-avoiding rectilinear steiner tree routings for delay and slack optimization

Obstacle Avoiding Rectilinear Clock Tree Construction with Skew Minimization

Similar Documents

An algorithm for obstacle-avoiding clock routing tree construction with multiple TSVs on a 3D IC

Rectilinear Steiner Clock Tree Routing Technique with Buffer Insertion in Presence of Obstacles

Clock Tree Skew Minimization with Structured Routing

Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion

Post-layout OPE-predicted redundant wire insertion for clock skew minimization

Critical-Trunk-Based Obstacle-Avoiding Rectilinear Steiner Tree Routings and Buffer Insertion for Delay and Slack Optimization

Bounded-Skew Clock and Steiner Routing Under Elmore Delay (1995)

Bounded-Skew Clock and Steiner Routing Under Elmore Delay (1995)

Critical-trunk based obstacle-avoiding rectilinear steiner tree routings for delay and slack optimization

Obstacle Avoiding Rectilinear Clock Tree Construction with Skew Minimization