NDLI: A Test Partitioning Technique for Scheduling Tests for Thermally Constrained 3D Integrated Circuits

Content Provider	IEEE Xplore Digital Library
Author	Millican, S.K. Saluja, K.K.
Copyright Year	2014
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Wisconsin-Madison, Madison, WI, USA (Millican, S.K.; Saluja, K.K.)
Abstract	Increasing design complexity coupled with new design and manufacturing techniques being used for modern integrate circuits is creating challenges for test environment. The goal of system-on chip (SoC) test scheduling has always been to reduce test application time. Added design constraints for SoC environment are making this scheduling more difficult. This difficulty is increased by manufacturing techniques like 3D stacked integrated circuits. Traditional test schedules for 3D stacked ICs can be either prohibitively long or may not exist without resorting to test partitioning. Partitioning methods proposed in literature have been ad hoc or simplistic. This paper presents a test partitioning method specifically designed for thermally constrained tests for the purpose of reducing test application time of 3D stacked integrated circuits under temperature constraint. The efficiency of the method is demonstrated by comparing it to the ad hoc methods previously investigated in the literature.
Sponsorship	IEEE Comput. Soc.
Starting Page	20
Ending Page	25
File Size	266073
Page Count	6
File Format	PDF
ISBN	9781479925131
ISSN	10639667
DOI	10.1109/VLSID.2014.11
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-05
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Schedules Hardware System-on-chip Benchmark testing Stacking Job shop scheduling Test scheduling 3D-IC SoC test temperature test test partitioning Test application time reduction
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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