NDLI: Highly robust Finfet based wide Fan-in dynamic OR gate with dynamic threshold voltage control

Content Provider	IEEE Xplore Digital Library
Author	Mahor, V. Pattanaik, M.
Copyright Year	2014
Description	Author affiliation: VLSI Design Lab., ABV-Indian Inst. of Inf. Technol. & Manage., Morena, India (Mahor, V.; Pattanaik, M.)
Abstract	Wide Fan-in dynamic OR gate has always been an integral part of high speed microprocessors. But dynamic logic gate suffers from low noise immunity. A weak PMOS keeper was introduced to increase the noise immunity. Keeper technique acts as a compensatory mechanism for charge loss due to leakage current and maintains high noise immunity while allowing leakage current through dynamic gate. A large size keeper is used for wide fan-in dynamic OR gate which allows large leakage current through the dynamic gate. This large leakage current unnecessarily results in large power dissipation which can be a critical factor for the microprocessors used in portable battery operated devices. Recently double gate Finfet has been reported to reduce leakage current effectively through it using threshold voltage control through back gate biasing technique. In this paper a new Finfet based wide fan-in dynamic OR gate has been proposed with reduced leakage and high noise immunity. This work reports a maximum leakage power reduction up to 70% while maintaining high noise immunity as compared to basic dynamic OR gate.
Sponsorship	IEEE Bombay Sect.
Starting Page	42
Ending Page	47
File Size	1169293
Page Count	6
File Format	PDF
ISBN	9781479924943
DOI	10.1109/CSCITA.2014.6839232
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-04-04
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Finfet Noise Logic gates FinFETs Noise immunity Threshold voltage Delays Dynamic logic Leakage currents
Content Type	Text
Resource Type	Article

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