NDLI: Stacked Active Loads For Low Power, High Speed GaAs Digital Circuits (SALFL)

Content Provider	IEEE Xplore Digital Library
Author	Mrunal, A.K. Shirasgaonkar, M.A. Patrikar, R.
Copyright Year	2006
Description	Author affiliation: Microelectron., Indian Inst. of Technol. Bombay, Mumbai (Mrunal, A.K.)
Abstract	The next generation of super-computers or base band circuits of advanced radio-telecommunication systems require very high speed switching circuits. Compound semiconductor materials such as gallium arsenide (GaAs) will play an important role in such systems. In GaAs devices the hole velocity is approximately 15-20 times lower compared to the electron velocity. This means that the complimentary structures are not as desirable in GaAs as they are in silicon. This leads to higher power consumption in these circuits. In this paper low power GaAs logic family stacked active load FET logic (SALFL) is proposed for the battery operated, portable wireless applications. In this proposed logic family, the ON and OFF state (leakage) currents are reduced using stacked active loads, there by reducing power consumption. GaAs circuits are preferred in high performance wireless front end circuits but are not used in base-band digital circuits due to their high current consumption and domination of silicon CMOS circuits in integrated circuit applications. But the CMOS technology already at 45nm node is plagued with the problem of sub-threshold leakage currents particularly severe in sub-100nm CMOS digital logic families. Both these problems can be effectively overcome using the GaAs SALFL logic family. Above low power technique is implemented with a standard enhancement/depletion mode FET processes and provides all the standard logic functions (Invertion, AND, OR, NOR, NAND etc) like other ( DCFL, SCF )logic families. This technique shows improved results with all GaAs devices like pHEMTs and MESFET. With this technique current consumption can be reduced while taking into account area requirements
Starting Page	1488
Ending Page	1491
File Size	3498717
Page Count	4
File Format	PDF
ISBN	1424403871
DOI	10.1109/APCCAS.2006.342504
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-12-04
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Gallium arsenide Digital circuits CMOS logic circuits Logic devices Silicon Energy consumption FETs CMOS digital integrated circuits CMOS technology Switching circuits Static Power Low Power GaAs Digital Circuits DCFL Dynamic Power
Content Type	Text
Resource Type	Article

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