NDLI: Low Power Current-Mode Algorithmic ADC in Half Flash (BCD)

Content Provider	IEEE Xplore Digital Library
Author	Chuenarom, S. Maitreechit, S. Roengruen, P. Tipsuwarnpron, V.
Copyright Year	2006
Description	Author affiliation: Dept. of Electron. Eng., South East Asia Univ., Bangkok (Chuenarom, S.; Maitreechit, S.)
Abstract	This paper presents a principle of analog to digital converter (ADC) based on current mode half flash (BCD). This circuit can be converted to 4-bit output at each moment, and multiple output bit numbers by serial connection. It uses a current injection technique to increase the speed of current mirrors, low power and algorithmic ADC application is presented. A current mode, the active current mirror and current comparators that controlled reference current by W/L ratio, has been used. Its feasibility agrees with simulation results of PSPICE program. The circuit design used CMOS 0.5mum which is capable to the slowest conversion time is less than 5.2nS, resulting in a conversion rate of more than 195 MHz, power consumed 1mW , input current 0-60 muA and single 2.5V supply
Starting Page	175
Ending Page	178
File Size	2823950
Page Count	4
File Format	PDF
ISBN	1424403871
DOI	10.1109/APCCAS.2006.342341
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-12-04
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power engineering and energy Mirrors CMOS technology Analog-digital conversion Circuit simulation SPICE CMOS digital integrated circuits CMOS analog integrated circuits Asia Circuit synthesis Power consumed ADC Active current mirror CMOS
Content Type	Text
Resource Type	Article

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