NDLI: Simultaneous Analysis of Capacitive Coupling and Leakage Noise in Nanometer Scale Circuits

Content Provider	IEEE Xplore Digital Library
Author	Tan, C.M. Chowdhury, M.H.
Copyright Year	2006
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Illinois Univ., Chicago, IL (Tan, C.M.; Chowdhury, M.H.)
Abstract	Traditional analysis deals with one noise source at a time. However, in nanometer scale circuits the evolving reality of multiple noise sources interacting with each other must be considered, since signal at an evaluation node will reflect the cumulative effect of all the active noise sources. This gives rise to a new approach - compound noise analysis. In this paper, an analysis of the combined effects of coupled and leakage noise is proposed. The proposed technique does not rely on simulation tools, and provides an insight to the behavior of individual noise sources when combined together on an evaluation node. It utilizes the recent BSIM4 models and addresses the issues of nanometer circuits with respect to parasitic capacitance, subthreshold and gate leakage noise in thin gate oxides below 15Aring. The model analyzes the noise effects dynamically with time, thus providing effective evaluation of signal integrity in high speed switching circuitry. Here coupling from multiple simultaneously switching aggressors, and leakage from more than one sources are modeled
Starting Page	2004
Ending Page	2007
File Size	3974408
Page Count	4
File Format	PDF
ISBN	1424403871
DOI	10.1109/APCCAS.2006.342281
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-12-04
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Coupling circuits Circuit noise Logic circuits Active noise reduction Circuit simulation Parasitic capacitance Gate leakage Voltage Subthreshold current Signal analysis nanometer compound noise gate leakage subtrheshold leakage BSIM4
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits

Leakage Reduction for Domino Circuits in Sub-65nm Technologies

7a-1 simultaneous control of subthreshold and gate leakage current in nanometer-scale cmos circuits.

A new noise-tolerant dynamic logic circuit design

High Speed Low Gate Leakage Large Capacitive-Load Driver Circuits for Low-Voltage CMOS

Reviews and Prospects of Low-Voltage Nano-Scale Embedded RAMs

Robust dynamic node low voltage swing domino logic with multiple threshold voltages

Simultaneous subthreshold and gate-oxide tunneling leakage current analysis in nanometer CMOS design

Dynamic noise analysis in precharge-evaluate circuits

Simultaneous Analysis of Capacitive Coupling and Leakage Noise in Nanometer Scale Circuits

Similar Documents

Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits

Leakage Reduction for Domino Circuits in Sub-65nm Technologies

7a-1 simultaneous control of subthreshold and gate leakage current in nanometer-scale cmos circuits.

A new noise-tolerant dynamic logic circuit design

High Speed Low Gate Leakage Large Capacitive-Load Driver Circuits for Low-Voltage CMOS

Reviews and Prospects of Low-Voltage Nano-Scale Embedded RAMs

Robust dynamic node low voltage swing domino logic with multiple threshold voltages

Simultaneous subthreshold and gate-oxide tunneling leakage current analysis in nanometer CMOS design

Dynamic noise analysis in precharge-evaluate circuits

Simultaneous Analysis of Capacitive Coupling and Leakage Noise in Nanometer Scale Circuits