NDLI: A High-Performance VLSI Architecture for Intra Prediction and Mode Decision in H.264/AVC Video Encoding

Content Provider	IEEE Xplore Digital Library
Author	Yu-Chien Kao Huang-Chih Kuo Yin-Tzu Lin Chia-Wen Hou Yi-Hsien Li Hao-Tin Huang Youn-Long Lin
Copyright Year	2006
Description	Author affiliation: Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu (Yu-Chien Kao; Huang-Chih Kuo; Yin-Tzu Lin; Chia-Wen Hou; Yi-Hsien Li; Hao-Tin Huang; Youn-Long Lin)
Abstract	The authors propose a high-performance hardware accelerator for intra prediction and mode decision in H.264/AVC video encoding. They use two intra prediction units to increase the performance. Taking advantage of function similarity and data reuse, the authors successfully reduce the hardware cost of the intra prediction units. Based on a modified mode decision algorithm, the design can deliver almost the same video quality as the reference software. The authors implemented the proposed architecture in Verilog and synthesized it targeting towards a TSMC 0.13mum CMOS cell library. Running at 75MHz, the 36K-gate circuit is capable of realtime encoding 720p HD (1280times720) video sequences at 30 frames per second (fps)
Starting Page	562
Ending Page	565
File Size	3624723
Page Count	4
File Format	PDF
ISBN	1424403871
DOI	10.1109/APCCAS.2006.342532
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-12-04
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Automatic voltage control Encoding Cost function Software algorithms Algorithm design and analysis Software quality Computer architecture Hardware design languages Circuit synthesis
Content Type	Text
Resource Type	Article

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