NDLI: Design Partitioning for Reducing Crosstalk Analysis Time

Content Provider	IEEE Xplore Digital Library
Author	Shrivastava, S. Parameswaran, H. Pratap, R.
Copyright Year	2006
Description	Author affiliation: Cadence Design Syst., India Pvt. Ltd., Noida (Shrivastava, S.; Parameswaran, H.; Pratap, R.)
Abstract	With increasing complexity of designs and reducing process nodes, the number of devices in designs has been rapidly rising. This has a dramatic impact on analysis of these designs, as the software and hardware are unable to analysis such designs "flat". The authors discuss a method for partitioning designs so that crosstalk analysis can be done on these smaller partitions and show that the technique cleanly divides the netlist into independent problem statements that can be analyzed parallely. The authors also show that the results of such independent runs can be merged and that the final report of the analysis is accurate (as compared to the analysis on the complete design). The authors show that the technique provides for dramatic reductions in runtime, and that the memory requirements of the design are also partitioned across the machines in approximately the same ratio as the size of the partitions themselves
Starting Page	796
Ending Page	800
File Size	199851
Page Count	5
File Format	PDF
ISBN	1424403871
DOI	10.1109/APCCAS.2006.342141
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-12-04
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Crosstalk Runtime Timing Information analysis Process design Software design Hardware Design methodology Parasitic capacitance Design engineering
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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