NDLI: A novel low-power and high-speed dynamic CMOS logic circuit technique

Content Provider	IEEE Xplore Digital Library
Author	Sharroush, S.M. Abdalla, Y.S. Dessouki, A.A. El-Badawy, E.-S.A.
Copyright Year	2009
Description	Author affiliation: Dept of Electricity, Fac. of Industrial Edu., Suez Canal Univ., Egypt (Abdalla, Y.S.; Dessouki, A.A.) \|\| Alex Higher Inst. of Eng. & Tech. / Fac. of Eng., Alex. Univ., Egypt (El-Badawy, E.-S.A.) \|\| Dept of Elect Eng, Fac. of Eng., Port Said, Suez Canal Univ., Egypt (Sharroush, S.M.)
Abstract	Domino CMOS logic finds a wide variety of applications due to their high speed and low device count. In conventional CMOS domino logic, either the dynamic-node capacitor, C is precharged to V during the precharge phase or predischarged to 0 V. The first precharging scheme is more suitable when logic “0” occurrence is more probable at the output due to the large saving in power consumption. On the other hand, the second predischarging scheme is more suitable when logic “1” is more probable at the output. In this paper, we will propose a novel technique to speed up the operation and minimize power consumption when there is an equal probability of occurrence of logic “0” and logic “1”. This technique depends on precharging the dynamic node to V/2 instead of V during the precharge phase. Then, during the evaluation phase, the dynamic-node voltage will be either increased to V or decreased to 0 V depending on the state of the inputs. This, of course, saves much of the time and power consumption because discharging the dynamic node from V/2 to 0 V is much faster and consumes less power consumption than discharging it from V to 0 V. Also, the discharging process and noise margin will be enhanced by virtue of the fact that the time interval during which the keeper combats the discharging process is relatively very small. The proposed technique will be simulated for the 0.13 µm technology with V=1.2 V. Simulation results show that about 75% was shaved from the cycle time for the case of “0” and “1” outputs at the expense of an additional silicon area.
Starting Page	1
Ending Page	8
File Size	1676663
Page Count	8
File Format	PDF
ISBN	9781424442140
ISSN	11106980
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-03-17
Publisher Place	Egypt
Access Restriction	Subscribed
Rights Holder	NRSC
Subject Keyword	CMOS logic circuits Logic devices Voltage Energy consumption Irrigation Capacitors Silicon Circuit noise CMOS digital integrated circuits CMOS memory circuits noise immunity dynamic logic low power high speed
Content Type	Text
Resource Type	Article

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